The present application relates generally to methods for forming semiconductor devices, and more specifically to devices such as fin field effect transistors (FinFETs) having air-gap spacers disposed between adjacent conductive elements.
A trend in the development of semiconductor manufacturing technologies has been to increase the density of devices per chip, and hence decrease the size of active structures as well as the distances between such structures. An increase in device density may advantageously affect device performance such as circuit speed, and may allow also for increasingly complex designs and capabilities. However, the decrease in size and the attendant increase in density may also generate undesirable effects, including unwanted capacitive coupling between adjacent conductive elements.
In response to an applied voltage across a first conductor, for instance, the resulting electric field may induce unwanted charge segregation in an unbiased, neighboring conductor. Capacitive coupling may also occur between a gate conductor and a source/drain region, e.g., source/drain contacts, resulting in charge segregation near the source/drain region rather than in the channel region of a transistor.